`timescale 1ns / 1ps module detect_0110(clk , rstb , din_bit , detect_out); input clk, rstb; input din_bit; output detect_out; reg [3:0] seq_reg; always @(posedge clk or...
`timescale 1ns / 1ps module cnt_4 (clk, rstb, cnt); input clk, rstb; wire [4:0] t; output [3:0] cnt; reg [3:0] cnt; initial cnt[0] <= 1'b0; assign cnt[0] ^ t[0]...
tb입니다.. module tb_bcd_add; reg [7:0] a, b; reg c0; wire [7:0] s; wire cout; bcd_add bcd_add(a, b, s, c0, cout); initial begin c0 = 0; for (a[7:4] = 4...
이걸 해야하는데 어떻게 하나요.. tb 입니다.. module tb_parity; reg [7:0] data wire parity_err; wire [8:0] trx_data wire [8:0] trx_data1;...
태그: verilog, veriloghdl, hdl, 전자전기공학
4비트 가감산기를 만드는 문제인데, sub = 0일떼 덧셈을, sub이 1일때 뺄셈을 수행하는겁니다.. 근데, 하위모듈로 Fulladder를...
`timescale 1ns / 1ps module lfsr_4bit (x_out, clk, presetb); input clk, presetb; output [4:1] x_out; reg [4:1] x_out; wire feedback; assign feedback = ~(x_out[4] ^ x_out[3]...
`timescale 1ns / 1ps module carry_select_adder(a, b, sum, c16); input [15:0] a; input [15:0] b; output [15:0] sum; output c16; assign {c1_12, s1_12} = a[15:12] + b...
`timescale 1ns / 1ps module rol(a, rol_amt, y); input [7:0] a; input [2:0] rol_amt; output [7:0] y; assign y[7:0] = (a[7:0] << rol_amt[2:0]) | (a[7:0] >> 8 - rol...
`timescale 1ns / 1ps module bcd2exc3(b,e); input [3:0]b; output [3:0]e; assign e[0] = ~b[0], e[1] = (b[0]&b[1])|(~(b[1]|b[0])), e[2] = ((~(b[1]|b[0]))&b[2]) | ((b[1]|b[0]...
`timescale 1ns / 1ps module bit_operations(a, y); input [31:0] a; output [31:0] y; assign y[31:24] = 8'h^a[31:24]; assign y[23:16] = 8'h11|a[23:16]; assign y[15...