verilog 카운터 오류..//코드 있음
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게시물 수정 , 삭제는 로그인 필요
`timescale 1ns / 1ps
module cnt_4 (clk, rstb, cnt);
input clk, rstb;
wire [4:0] t;
output [3:0] cnt;
reg [3:0] cnt;
initial cnt[0] <= 1'b0;
assign cnt[0] ^ t[0]
assign t[0] = 1;
assign t[4] = (cnt[3] & t[3]);
assign t[3] = (cnt[2] & t[2]);
assign t[2] = (cnt[1] & t[1]);
assign t[1] = (cnt[0] & t[0]);
always @(posedge clk or negedge rstb) begin
if (!rstb) cnt[3:0] <= 4'h0;
else if (t[0]==1) cnt[3:0] <= ~(cnt[3:0]);
else cnt[3:0] <= cnt[3:0];
end
endmodule
module tb_cnt_4;
reg clk, rstb;
wire [3:0] cnt;
cnt_4 u0(clk, rstb, cnt);
initial clk = 0;
always #5 clk = ~clk;
initial begin
#0 rstb = 0;
#10 rstb = 1;
#300 $stop;
end
endmodule
뭐가문제인가요? 한발자국만 가면 될것같은데..
`timescale 1ns / 1ps
module cnt_4 (clk, rstb, cnt);
input clk, rstb;
wire [4:0] t;
output [3:0] cnt;
reg [3:0] cnt;
initial cnt[0] <= 1'b0;
assign cnt[0] ^ t[0]
assign t[0] = 1;
assign t[4] = (cnt[3] & t[3]);
assign t[3] = (cnt[2] & t[2]);
assign t[2] = (cnt[1] & t[1]);
assign t[1] = (cnt[0] & t[0]);
always @(posedge clk or negedge rstb) begin
if (!rstb) cnt[3:0] <= 4'h0;
else if (t[0]==1) cnt[3:0] <= ~(cnt[3:0]);
else cnt[3:0] <= cnt[3:0];
end
endmodule
module tb_cnt_4;
reg clk, rstb;
wire [3:0] cnt;
cnt_4 u0(clk, rstb, cnt);
initial clk = 0;
always #5 clk = ~clk;
initial begin
#0 rstb = 0;
#10 rstb = 1;
#300 $stop;
end
endmodule
뭐가문제인가요? 한발자국만 가면 될것같은데..
#verilog 카운터 #verilog 클럭 카운터 #동기식 카운터 verilog
