베릴로그 질문있어요
-
게시물 수정 , 삭제는 로그인 필요
module tnn(clk, me, pre, sl, slb, wl, se);
input clk, me;
output reg pre, sl, slb, wl, se;
always @(posedge clk) begin
pre <= ~me;
sl <= me;
slb = ~sl;
wl <= sl;
se <= wl;
end
endmodule
module tnn_top();
reg clk, me;
wire pre, sl, slb, wl, se;
tnn uut(clk, me, pre, sl, slb, wl, se);
initial begin
clk=0;
me=0;
#5 me=1;
end
always begin
#5 clk=~clk;
end
endmodule
사진처럼 구현해야 하는데 어떻게 해야할지 잘 모르겠습니다
![](https://img-api.cboard.net/img_n.php?image_url=https://kin-phinf.pstatic.net/20230102_119/1672641260712tjKV3_JPEG/IMG_6811.jpg)